Tile gx instruction set ideas

This is an IDA processor module for the Tile-GX processor architecture. The code leverages libbfd and libopcodes for translating to assembler. The TILE-Gx9, fabricated in a 40 nanometer process, integrates nine 64-bit processor cores along with a robust set of I/O ports and memory.Automatic and manual hitless reference switching options are supported. LOS behavior can be set to support gapped or un-gapped clocks. Instruction set feature. TILE instruction set architecture is 3 way VLIW. Two or three instructions are in a single 64bit word which is in.